1. Field of the Invention
This invention relates generally to a comparator circuit, and in particular to a comparator circuit which is capable of performing high-speed as well as reliable operation and has particular applicability to an analog to digital converter.
2. Description of the Prior Art
There is illustrated in FIG. 1 a typical prior-art analog to digital converter (A/D converter). The A/D converter includes a reference voltage supply 504, a plurality of comparator 501 to 50n, and a decoder 505 which is connected in common to the outputs of the comparator 501 to 50n. In operation, the voltage generated by the reference voltage supply 504 is divided by series connected resistor 601 to 60(n+1), and divided voltages are supplied to one inputs of the comparators 501 to 50n. Voltage signals V.sub.2 to be converted into digital signals are applied to the other inputs of the comparators 501 to 50n. Each of the comparators 501-50n compares the input voltage levels at one and the other inputs, and supplies a voltage signal representative of the compared results to the decoder 505, which in turn produces a digital signal proportional to the compared results.
FIG. 2 shows a circuit configuration of a prior-art comparator circuit. The type of the comparator circuit shown in FIG. 2 is disclosed, for example, in Digests of Technical Papers pp. 34-35 presented in International Solid-State Circuits Conference of February 1985.
Referring to FIG. 2, the comparator circuit includes an input terminal 6 to receive a first input voltage V.sub.1, and an input terminal 7 to receive a second input voltage V.sub.2, an amplifier section 4 having a capacitor 1, and an inverters 5 connected to the output of the amplifier section 4. A switching circuit 8 is inserted between the input terminal 6 and the amplifier section 4, and another switching circuit 9 is provided between the input terminal 7 and the amplifier section 4. The amplifier section 4 includes a capacitor 1, one electrode of which is connected to a node Na to receive signals from the switching circuit 8 or 9. The capacitor 1 has the other electrode connected to a node Nb. The amplifier section 4 also includes an inverter 2 coupled to the node Nb and a switching circuit 3 connected across the inverter 2. The inverter 5 provides at its output terminal 10 voltage signals of two different values representative of compared results.
Now the operation of the comparator circuit is described, assuming that: the inverters 2 and 5 have identical transfer characteristics; the switching circuits 8 and 9 are controlled to turn on in an alternate fashion; and the switching circuit 3 is controlled to turn on in synchronization with the turning-on of the switch circuit 8.
During the first half of an operating cycle, the switch circuits 8 and 3 are turned on, while the switch circuit 9 is turned off. As a result, an input voltage V.sub.1 is supplied to the node Na. A turning-on of the switch circuit 3 across the inverter 2 applies a shunted voltage Vs to the node Nb. The shunted voltage Vs is next referred to.
Graphs in FIG. 3 illustrate input-output characteristic (or transfer characteristics) of the inverter 2. The abscissa gives the input voltage of the inverter 2 and the ordinate is the output voltage of the same inverter. The curve a shows the input-output characteristics of the inverter 2, while the straight line b indicates the input-output characteristics of the inverter when its input voltage Vi is equal to its output voltage V.sub.0. The shunted voltage Vs is equal to the voltage represented by the point c where the curve a and the line b cross.
Thus, during the first half of the operating cycle, the node Nb is charged up to the potential of Vs-V.sub.1 with respect to the node Na.
During the second half of the operating cycle, the switching circuits 8 and 3 are turned off, while the switching circuit is turned off, and a voltage V.sub.2 is applied to the node Na. Due to the off state of the switching circuit 3, the node Nb is kept at a high impedance. Thus, if the effect of parasitic capacitance can be ignored, the potential difference Vs-V.sub.1 produced between the nodes Na and Nb is maintained at the beginning of the second half of the operating cycle. Under the circumstances, as the voltage applied to the node Na changes from V.sub.1 to V.sub.2, the voltage at the node Nb varies by V.sub.2 -V.sub.1. Consequently, the node Nb is brought to a potential of Vs-V.sub.1 +V.sub.2.
As can be seen in FIG. 3, the output of the inverter 2 is biased to voltage Vs at point c where higher amplification is obtained. This ensures that, even if the shift in the input voltage V.sub.2 -V.sub.1 of the inverter 2 is very small during the second half of the operating cycle, its output voltage exhibits a relatively large amount of change. When the amplification of the inverter is defined -A, its output voltage V.sub.01 is given as follows: EQU V.sub.01 =Vs-A(V.sub.2 -V.sub.1) (1)
On the other hand, since the inverter 5 possesses the input-output characteristic identical to the inverter 2, the inverter 5 produces a voltage Vs in the first half of the operating cycle. Accordingly, during the second half of the operating cycle, the shift in the output voltage -A (V.sub.2 -V.sub.1) of the inverter 2 is further amplified by the inverter 5. Assuming that the inverter 5 has the same amplification -A as the inverter 2, the output voltage V.sub.02 of the inverter 5 is given as: EQU V.sub.02 =Vs+A.sup.2 (V.sub.2 -V.sub.1) (2)
As has been explained hereinabove, the comparator circuit generates the voltage Vs during the first half of the operating cycle, and produces a voltage signal in proportion to a potential difference between the input voltages V.sub.1 and V.sub.2 during the second half of the operating cycle. In other words, the comparator provides a logic signal "H" or "L" representative of the result obtained by comparing the input voltage V.sub.1 with the input voltage V.sub.2.
As stated previously, the inverter 2 produces the voltage Vs with a predetermined delay, followed by the generation of the voltage Vs by the inverter 5 with a transfer delay between its input and output terminals. These delays do little harm when the comparator circuit operate at lower speeds, but give rise to some problems when the comparator operates at higher speeds. In a high-speed operation of the comparator, even if the inverter 2 produces a voltage Vs during the first half of the operating cycle, the comparator operation proceeds into the second half of the operating cycle with the inverter 5 not generating the potential Vs. This may result in an erroneous operation, which will be explained in detail.
FIG. 4 is a timing chart showing changing output voltages of the inverters 2 and 5 as the comparator circuit operates at high-speeds. In FIG. 4, four operating cycles T1 to T4 of the comparator circuit are shown. During the operating cycles T1 and T2, the input voltage V.sub.1 is lower than the input voltage V.sub.2, while in operating cycles T3 and T4, the input voltage V.sub.1 is higher than the input voltage V.sub.2. Time intervals Ta1 to Ta4 correspond to the first half of respective operating cycles, and time intervals Tb1 to Tb4 to the latter half of respective operating cycles.
In the operating cycles T1 and T2 where the input voltage V.sub.1 is lower than the input voltage V.sub.2, the output voltage V.sub.01 of the inverter 2 rises close to the voltage level Vs during the time intervals Ta1 and Ta2, and it falls gradually off the voltage level Vs during the time intervals Tb1 and Tb2. Theoretically, the output voltage V.sub.01 reaches Vs-A (V.sub.2 -V.sub.1).
On the other hand, the output voltage V.sub.02 of the inverter 5 does not fall down to the level of the voltage Vs not only through the time intervals Ta1 and Ta2, but through the time intervals Tb1 and Tb2. With the input voltage V.sub.1 lower than the input voltage V.sub.2 during the operating cycles T1 and T2, the output voltage V.sub.02 of the inverter 5 higher than the voltage Vs does not prevent the generation of accurate comparison results.
However, during two successive cycles of operation where the relative relations between the input voltages V.sub.1 and V.sub.2 reverse themselves as demonstrated in the operating cycles T.sub.2 and T.sub.3, the above stated voltage conditions lead to erroneous operations to be described next. The output voltage V.sub.02 is higher than the voltage Vs at the end of the time interval Tb2. During the operating cycle T3, the output voltage V.sub.02 of the inverter 5 fails to reach the level of the voltage Vs because of the input voltage V.sub.1 higher than the voltage level V.sub.2. In the beginning of the time interval Tb3, the input voltage V.sub.02 starts to fall off, but it fails to drop enough to be lower than the voltage Vs even at the end of the time interval Tb3 due to the fact that the output voltage V.sub.02 of the inverter 5 is substantially higher than the voltage Vs at the start of the time interval Tb3. Phrased differently, during the operating cycle T3, the inverter 5 generates an output voltage V.sub.02 higher than the voltage Vs despite the input voltage V.sub.1 being higher than the input voltage V.sub.2. Thus, the comparator fails to provide accurate comparison results in the operating cycle T3.